1. Field of the Invention
The present invention relates to a method for arranging logical cells in a semiconductor integrated circuit by utilizing a computer, and, in particular, relates to a method for arranging logical cells to optimize operational characteristics such as delay time in a semiconductor integrated circuit.
2. Description of the Background Art
Conventionally, a gate array method which is also called a master slice method has been well known to design a semiconductor integrated circuit in a master chip.
In the gate array method, input/output terminal cells and basic cells respectively consisting of a prescribed number of transistors are regularly arranged in the master chip before gates of the cells are interconnected so as to satisfy design conditions given by a user, so that the semiconductor integrated circuit consisting of the cells with specific functions is manufactured.
A wafer in which the basic cells are merely arranged without interconnecting the cells before a wiring process is implemented is generally called a master wafer. In addition, a process for interconnecting the basic cells in the wiring process and for manufacturing a specialized circuit such as an inverter is called a personalization process.
Therefore, a user can arbitrarily select a prescribed number of basic cells to manufacture logical cells such as an inverter, an NAND circuit and a flip flop circuit in the personalization process.
In addition, the logical cells are interconnected by the wiring process to manufacture a standard circuit frequently utilized. The standard circuit is called a macro-cell, and many types of standard circuits are prepared as a library. Therefore, the user can arbitrarily select the standard circuits to efficiently design a semiconductor integrated circuit.
FIG. 1 is a plane view of a master chip consisting of a master wafer. As shown in FIG. 2, input/output terminal cells 12 are arranged at the peripheral regions of a master chip 11. In addition, an array region 13 for arranging macro-cells is positioned at the central region surrounded by the input/output terminal cells 12.
In the above configuration, a user selects desired type of macro-cells by a necessary number according to design conditions such as circuit connection conditions given by the user. Thereafter, the user interconnects the macro-cells according to the design conditions to implement the personalization process.
In cases where the gates of the macro-cells can be spread over the entire array region 13 in the gate array method, the entire area of the array region 13 can be utilized to arrange the macro-cells so that each macro-cell can be set at an arbitrary position. In this case, the wires interconnecting the macro-cells pass through regions not occupied by the macro-cells. Or, the wires pass through the peripheral regions of the macro-cells which are not occupied the logical cells composing the macro-cell.
A layout process for designing the arrangement of the macro-cells has been recently implemented by utilizing a computer to manufacture a large scaled semiconductor integrated circuit because the arrangement of the macro-cells is impossible to implement by hand.
The arrangement of the macro-cells requires a large scaled integration in the layout process. In addition, the operational conditions given by the user must be satisfied in the layout process. Therefore, many types of conventional methods for improving the integration of the macro-cells have been proposed and implemented. However, any type of conventional method cannot optimize the operational characteristics such as an operating frequency and operating reliability, while the conventional method can achieve the high integration of the macro-cells.
The optimization of a signal route in the integrated circuit is generally efficient to improve the operating frequency of the integrated circuit arranged on the array region 13 because the length of the signal route influences on the operational characteristics such as the operating frequency. Therefore, many conventional methods have been proposed to improve the operational characteristics of the integrated circuit. In short, the improvement is directed to decrease the delay time occurring in the signal route.
FIG. 2A shows a signal route before the operational characteristics are improved. A signal route 20 arranged in the array region 13 connects a source 21 with a sink 22. The source 21 is an input terminal to receive a signal provided to the signal route 20, and the sink 22 is an output terminal to provide the signal to a following circuit. The signal route 20 generally passes through a plurality of nets N1 to N9. Each net consists of a plurality of macro-cells 23 and signal lines for respectively connecting the macro-cell 23. The macro-cells 23 in the net are equipotential because the macro-cells 23 are directly interconnected through the signal lines. The signal lines of all the nets compose the signal route 23. The value of the delay time depends on the total length of the signal route 23. Therefore, the delay time of the signal route 23 is calculated by adding the delay time occurring in the signal lines of each net.
The operational characteristics of the integrated circuit are determined by arranging the macro-cells and the logical cells in the array region 13 in initial steps of the layout design such as a floor plan step and an arrangement step. That is, the logical cells such as and RAM and the macro-cells are roughly positioned at the array region 13 in the floor plan before the cells are arranged in detail in the arrangement step. Therefore, the operational characteristics are not varied so much unless considerable roundabout routes are taken to interconnect the macro-cells in a wiring step following the arrangement step. Accordingly, the user must consider the arrangement of the macro-cells in the initial steps so as to satisfy the operational characteristics.
An arrangement method for arranging the macro-cells by utilizing the timing analysis of the integrated circuit has been proposed (A. E. Dunlop, et al, "Chip Layout Optimization Using Critical Path Weighting", Proc. 21st DAC, pp.133-136, 1984). That is, a critical path equivalent to the signal route not satisfying the given operational characteristics is selected before each net composing the critical path is weighed by a weighing value according to the prescribed order of priority. Thereafter, the delay time of the signal lines in each net is reduced by arranging the macro-cells for each net. In this case, the layout of the nets is not changed.
FIG. 2B shows the signal route after the operational characteristics are improved by the arrangement method, the total length of the signal route being minimized by the arrangement method to improve the operational characteristics.
As shown in FIG. 2B, the signal lines formed by connecting the macro-cells which are initially positioned in the array region 13 as shown in FIG. 2A is minimized for each net by implementing the arrangement method. However, even though the length of the signal lines is minimized for each net, the length of the signal route consisting of the signal lines is not changed so much because the curves and the meanders of the signal route still remain.
Therefore, though the arrangement of the signal lines composing the net is optimized in the arrangement method, the arrangement of the nets is not optimized so that the optimization for decreasing the delay time of the signal route cannot be implemented. In other words, the unnecessary curves and meanders of the signal route cannot disappear. That is, in cases where the unnecessary curves and meanders of the signal route remains, the length of a main signal route connecting macro-cells 23 positioned between the nets is not optimized even though the total length of the signal lines is minimized for each net. Therefore, the decrease of the total delay time of the signal route is set a limit.
Accordingly, the optimization of the length of the main signal route is important as well as the minimization of the total length of the signal lines in the net.
Another arrangement method for arranging the macrocells has been proposed (Yasushi Ogawa, et al, "Efficient Placement Algorithm Optimizing Delay for High-Speed ECL Masterslice LSI's", proc. 23rd DAC, pp.404-410, 1986). That is, the restriction of the total length of the signal lines is determined by utilizing the timing analysis of the integrated circuit for each net. The timing analysis is implemented by utilizing an arrangement algorithm based on a two-division improvement. Thereafter, the allowable size of the net estimated by the restriction is compared with the size of a region to be divided in two before a weight is added to the net according to the result of the comparison.
In the above arrangement method, the optimization of the length of the signal route is not guaranteed. In addition, the number of restrictions becomes extremely large in cases where the critical path equivalent to the signal route consists of a large number of nets. Therefore, the operational characteristics improved by the two-division deteriorates so that the integration of the semiconductor circuits largely deteriorates. Moreover, in cases where the restriction relating to a plurality of nets exists, the critical path cannot be optimized because only the restriction given to each net can be considered. In other words, a plurality of nets are not simultaneously optimized.
Another arrangement method has been proposed (Masuyuki Terai, et al, "A New Min-Cut Placement Algorithm for Timing Assurance layout Design Meeting Net Length Constraint", proc. DAC, pp.96-102, 1990). That is, the constraint of the nets in the critical path is given by utilizing the min-cut placement method.
In the above arrangement method, in cases where the constraint relating to a plurality of nets exists, the critical path cannot be optimized.
Another arrangement method has been proposed (Michael A. B. Jackson, Arvind Srinivasan, E. S. Kuh, "A First Algorithm for Performance-Driven Placement", proc. ICCAD pp.328-331, 1990). That is, each net is initially given the delay constraint. Thereafter, the optimization of the length of the signal lines is implemented for each net while the constraint is renewed.
In the above arrangement method, the route of the critical path equivalent to the signal route cannot be optimized because the constraint is added for each net.
As mentioned above, the improvement of the operational characteristics is set a limit because the optimization of the length of the signal route is not guaranteed. In other words, the operational characteristics of the semiconductor integrated circuit cannot be completely improved in cases where the length of the signal lines connecting the macro-cells is minimized for each net.